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Altera_Forum
Honored Contributor
Honored ContributorDifferent results on hardware compared to simulator
I'm having trouble when I run my code on the actual Cyclone III FPGA. In the simulator it works fine. I have set up state machines to make sure that clock signals to registers are occurring after ple...
Altera_ForumHonored Contributor
Honored ContributorThe most important issue is that a signal is viewed as clock if it is used to edge trigger any register since it will be connected to clk port of flips.
The safest thing for a beginner is one clock for all registers. As to tristating inside fpga: you don't need that as it is going to be implemented as muxes and will complicate coding on you.
