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Altera_Forum
Honored Contributor
Honored ContributorDifferent results on hardware compared to simulator
I'm having trouble when I run my code on the actual Cyclone III FPGA. In the simulator it works fine. I have set up state machines to make sure that clock signals to registers are occurring after ple...
Altera_ForumHonored Contributor
Honored ContributorI did try setting up timing yesterday and used the wizard to generate an sdc file. It looks much like what you sent me, but with a couple of different set_false_path statements that I don't fully understand:
set_false_path -from -to
set_false_path -from -to
