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Altera_Forum's avatar
Altera_Forum
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8 years ago

Difference between "logic" and "bit" data types.

Hi all, As we know "logic" data type has 4 states = 0, 1, X & Z, where as "bit" has only 2 states = 0 & 1. Generally we can see use of "logic" as data type for all kind of signals on interne...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
8 years ago

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std_logic data type has 9 states: "U, X, 1, 0, Z, W, L, H, - "

u: Uninitialized

x: Unknown

1: Logic 1

0: Logic 0

Z: High impendance

W: Weak signal, can't tell if it should be 0 or 1

L: Weak signal that should probably go to 0

H: Weak signal that should probably go to 1

-: Don't care.

In your example, U state can be useful if you forget to initialize a signal in your component testbench.

--- Quote End ---

The OP is asking about Verilog. Std_logic is a VHDL concept.