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New Contributor

6 years ago

Did I set up input timing constraints correctly?

I have both clock and data coming from external chip: input_clock, input_data. Datasheet says setup time 3ns, hold time 1ns. Can you please check if these constraints are correct? I believe so but t...

JSmit123

New Contributor

6 years ago

What would be the correct constraints? I added more details below

IDeyn

Contributor

6 years ago

Hi JSmit123!

I agree with sstrell last post, it is not a simple task, so you need some reading for deeper understanding of Source Synchronous Interface Constraints.

In my opinion best resourse on that topic - https://fpgawiki.intel.com/wiki/index.php?title=File:Source_Synchronous_Timing.pdf by Ryan Scoville.

To write a proper sdc constraints in your case you can choose from number of methods.

Hope that helps.

Best Regards,

Ivan

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Did I set up input timing constraints correctly?

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