Devide in VHLD

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The output is not valid until CNT is 2 anyway, so until then all signals are rubbish.

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Valid result or not, a registered output can't change arbitrarily. Or the design's timing is completely broken.

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Because Modelsim does not support for LPM library. And when I use multiply command directly, the result's not true with the negative number.

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Last time I used it, all LPM libraries simulated fine in ModelSim. Sorry, I also don't understand about the negative number problems. At least, I wasn't aware of it (since Quartus V2.0).

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Last time I used it, all LPM libraries simulated fine in ModelSim. Sorry, I also don't understand about the negative number problems. At least, I wasn't aware of it (since Quartus V2.0).

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Really?

LPM library took me a lot of time. I use Modelsim plus 5.7d and Quartus 7.2

Could you help me step by step with it?

All Quartus specific libraries (LPM and device specific) have been installed during initial ModelSim installation (some ModelSimDE6.1 or 6,2 version). Unlike when simulating Verilog, I don't remember missing library issues with VHDL designs. But I don't have ModelSim installed on my computer now and can't check these problems.

An additional remark related to your previously posted waveform. You didn't ever mention a device family. The timing could be explained if either belonging to a very slow logic family, or if the synthesis options in effect would allow to move an output register.

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You can precompile most libraries in Modelsim.

Usually altera_modelsim will have these lpm/altera_mf libraries ready from installation.

Otherwise you can precompile as follows:

go to modelsim => compile => set library name to lpm => navigate to altera folders that contain 220pack.vhd/220model.vhd. select them and compile.

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I don't know, why menu compile of my Modelsim software is not active. I can not choose it.

I add 220pack.vhd/220model.vhd to my project and compile => not ok

I can not make new library from "a new library and a logical mapping to it" or "a map to an existing library" to folder that contain 220pack.vhd/220model.vhd file.

This is my video:

Add 220pack.vhd/220model.vhd to project and compile them: http://www.mediafire.com/?44i1sj5bgnkduty

Can not make new library: http://www.mediafire.com/?53zp5xyrpd2zdjk

Can not make new library: http://www.mediafire.com/?krc4l1g5u5uyayj

Could you check it for me.

Thank alot

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All Quartus specific libraries (LPM and device specific) have been installed during initial ModelSim installation (some ModelSimDE6.1 or 6,2 version). Unlike when simulating Verilog, I don't remember missing library issues with VHDL designs. But I don't have ModelSim installed on my computer now and can't check these problems.

An additional remark related to your previously posted waveform. You didn't ever mention a device family. The timing could be explained if either belonging to a very slow logic family, or if the synthesis options in effect would allow to move an output register.

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I'm sorry when i forgot mention a device family.

I use DE2-70 (Cyclone II) - EP2C70F896C6

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Usually altera_modelsim will have these lpm/altera_mf libraries ready from installation.

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Hi Kaz

How's about altera_modelsim?

It's a single software or built-in with quartus software?

Why I don't see it in my computer?

Thank you very much.