device size disproportional number of user IO pins

I doubt there's any documentation on it. I/O counts are obviously an important feature, and it's certainly annoying to see counts go down as you go to a larger device. (If you plan for possible migration using the migration devices option, then you're limited to the lower amount across all devices). That being said, it all seems pretty logical that all the necessary GND/PWR/Control/Dedicated signals are connected first, since they have to be, and the rest are used for I/O. As the die grows larger, more GND/PWR I/O are needed, and hence user I/O half to be sacrificed.

As for comparing to Xilinx, who knows, but I'd be curious if you found out. Assuming the larger devices need more GND/PWR connections, yet the number are consistent throughout the family, then either the smaller devices are "over powered" (wasteful but not bad) or the larger devices are "under powered"(bad). Or maybe something else is at play. Either way, the numbers aren't going to change and you'll have to design within those constraints. Hope that helps.