device size disproportional number of user IO pins

Your post but would be better understandable, if you tell what you are exactly missing.

To start with a trivial fact. While the number of LEs is a function of chip area, the maximum I/O pin count only grows according to it's edge length, because bond pads and I/O cells have to be placed at the chip border.

Altera FPGAs are always designed to allow vertical migration within a particular package type. A larger chip with more IOs has also more ground pins. Apparently to provide maximum signal integrity, Altera decided to bondout all (or at least more) available ground pads. This results in less available IO's for the larger device in the same package.