detecting rising and falling edge

Here's what you need to do;

1) Route your serial clock through a dual-DFF synchronizer that is clocked by your main clock. Lets say the input is called sclk, and the output is called sclk_sync.

2) Route sclk_sync through another DFF, and call that sclk_dly.

3) Draw yourself a timing diagram of sclk_sync and sclk_dly. What logic operation do you need to detect the rising edge and falling edge? Hint, what does 'sclk_sync and sclk_dly' look like, how about 'sclk_sync and not sclk_dly'? One combination will give you the rising-edge, while another will give you the falling-edge.

4) Create logic to enable/disable a counter clocked by clk, where the enable/disable logic is based on the rising-edge/falling-edge logic.

Try to figure the logic out. If you get stuck, ask for help.

Cheers,

Dave