Honored ContributorHi to all,
for my little project, I need to manage the output pin of any FPGA placing them at high impedance. This is not a problem, I can do it with MAX10 and Cyclone IV. However I would need to detect if an input pin is a logic level 0, 1 or disconnected (High-Z). It is possible?
Honored ContributorAn unconnected High Z Pin gives you only true or false to the internal logic. In order to get the High Z State you need some additional circuitry.
Some ideas:Honored ContributorAnother idea is to use an "oscillating" bus hold. Use the inverted latched input value as driver for a resistor to the input as programmable pullup/pulldown. In case the external Pin is tristate you have implemented a toggle flipflop with f/2 this way.
In case the external Pin is push/pull you get "1" or "0". The disadvantage is that you need two Pins for this ...Honored ContributorHi DUESTERBERG, thanks for your aswers!
--- Quote Start ---Honored Contributor1) create a pattern on the driving Pin (clock, prbs, ...) and compare the input with the driving signal. If both are the same over some time the Pin is High Z.
2) you are more flexible with a FPGA Pin, and you know what you are driving (expected data), this depends on what you have available on you board.Honored ContributorUsually, for busses that are biderectional, there is a master somewhere that knows what direction the bus is driving at all times. For your inputs, there would be a write_enable signal or similar so you know whether the input pins should be Z or not.
Using some external circuitry like those described above seems rather over complicated.Honored ContributorYou are absolutely right, but i don't know the application. Maybe it is something like a hardware in the loop test, not just a "normal" bus ...
