Detect high impedance on the input pin

An unconnected High Z Pin gives you only true or false to the internal logic. In order to get the High Z State you need some additional circuitry.

• connect you pin to VCCIO/2 with a 10k resistor and use a window comparator to detect this level. Maybe this is possible with differential LVDS inputs.

• use a external window comparator with 2 digital outputs to the FPGA

• connect your pin to another toggling pin with a 10k resistor and try to detect this frequency or pattern (eg: 1MHz)

• use a RC combination from your external signal to the FPGA bidir PIN and use short test pulses (with output enable) to charge/discharge the capacitor. The time constant is different depending on the external Level (0, Z, 1)

• use a RC combination from your external signal to the FPGA bidir PIN and use short test pulses (with output enable) to discharge the capacitor and a weak pullup to charge
  measure the time the pin needs to go high:
  short time: Pin is connected to "1"
  longer time: Pin is connected to "Z"
  never: Pin is connected to "0"