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Altera_Forum's avatar
Altera_Forum
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10 years ago

Design flow problem with PCIe IP

Hello,

I'm working on a PCIe design. However there're different design flows, such as Megawizard and Qsys, and different IP interfaces(avalon MM and ST). I'm new to both Qsys and PCIe. My FPGA design's function is mainly transmiting data to PC. Which flow and interface is better?

I read the application note which introduces an example design with Qsys. I haven't see anything about Nios II processor. Is it necessary for a Qsys design?

Best Regards,

Cycad Hsu

3 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    If you use the latest Quartus 15.1, there is not Megawizard flow anymore. Everything is done thru Qsys.

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    --- Quote Start ---

    If you use the latest Quartus 15.1, there is not Megawizard flow anymore. Everything is done thru Qsys.

    --- Quote End ---

    Is Nios II processor required in Qsys flow design?