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Altera_Forum
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10 years ago

Design flow problem with PCIe IP

Hello, I'm working on a PCIe design. However there're different design flows, such as Megawizard and Qsys, and different IP interfaces(avalon MM and ST). I'm new to both Qsys and PCIe. My FPGA ...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
10 years ago

If you use the latest Quartus 15.1, there is not Megawizard flow anymore. Everything is done thru Qsys.