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Altera_Forum's avatar
Altera_Forum
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13 years ago

delaying state transitions in FSM

Hello,

I am interested to know about the various methods for delaying the state transitions between different states in a FSM.

Currently I use the clock signal in my design to drive a counter, which is compared with a max_count (say equal to 10). If they are equal, then I enable the signal. So I delay the transition by 10 cycles.

// here is a scrap code of my implementation

max_count= 'd10;

always@(posedge clk)

if(reset)

begin//{

count_enable<= 'b0;

count<='b0;

end//}

always@(posedge clk)

if(count_enable)

count<= count+'b1;

else

count<= 'b0;

// in the state machine inside each states

always@(*)

...

switch(ps)

idle:

state1:

if((count==max_count)&(..condition..)

ns= state 2;

state 2:

**********

I wish to know if my approach is right. And would also like to know it there is some other way to implement the delay between states. Any suggestion is appreciated.

thanks,

Manihatn

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Using a counter is a good way.

    On occasion, I add states just to make up for the delay.

    You can also think of using a shift register.

    But in general, a counter is what you want.

    Weather your particular way is the best or not.. depends on your actual needs.

    You just have to make sure you reset and enable the counter when you need.

    For example, in your code I only see the counter being reset to zero once. So, it will only delay the state1 -> state2 transition once.

    Also, do you guarantee that "condition" is kept true during the 10 cycles? If not, you may have another problem there...
  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    13 years ago

    Thanks for the insight...

    --- Quote Start ---

    You can also think of using a shift register.

    --- Quote End ---

    Will be happy if you can help me with some source. Would really like to try, just out of interest.

    --- Quote Start ---

    For example, in your code I only see the counter being reset to zero once. So, it will only delay the state1 -> state2 transition once.

    --- Quote End ---

    I use an enable signal to reset the counters. For example, I enable the signal in state 1, which triggers the counter, which is checked against the max_count value in state 2. If condition matches, I disable the signal which resets the counter.

    --- Quote Start ---

    Also, do you guarantee that "condition" is kept true during the 10 cycles? If not, you may have another problem there...

    --- Quote End ---

    I am not sure if the condition refers to the state of the signals

    regards,

    Manihatn