Forum Discussion
Altera_Forum
Honored Contributor
13 years agoThanks for the insight...
--- Quote Start --- You can also think of using a shift register. --- Quote End --- Will be happy if you can help me with some source. Would really like to try, just out of interest. --- Quote Start --- For example, in your code I only see the counter being reset to zero once. So, it will only delay the state1 -> state2 transition once. --- Quote End --- I use an enable signal to reset the counters. For example, I enable the signal in state 1, which triggers the counter, which is checked against the max_count value in state 2. If condition matches, I disable the signal which resets the counter. --- Quote Start --- Also, do you guarantee that "condition" is kept true during the 10 cycles? If not, you may have another problem there... --- Quote End --- I am not sure if the condition refers to the state of the signals regards, Manihatn