Delaying output of a module to close timing

Have you thought about using the multicycle path construct in TimeQuest to tell the optimizer that your logic block between the two registers takes more than one cycle to compute? In your case you would set the multicycle multiplier to a value of '2' (assuming a 10ns clock and your multiplier takes 20ns minus register setup/output times to compute).

See: https://www.altera.com/support/support-resources/design-examples/design-software/timequest/tq-multicycle-path.html

and

https://www.altera.com/support/support-resources/design-examples/design-software/timequest/exm-tq-sdc-exceptions.html

(https://www.altera.com/support/support-resources/design-examples/design-software/timequest/exm-tq-sdc-exceptions.html)

You need constraints something like:

set_multicycle_path -from [get_keepers {a_reg2

[*] b_reg2

[*]}] -to [get_keepers {out

[*]}] -setup 2

set_multicycle_path -from [get_keepers {a_reg2

[*] b_reg2

[*]}] -to [get_keepers {out

[*]}] -hold 1

where the FROM and TO operands need to be expanded to the full path to the appropriate register instances (including module instance name).

Setup 2 / Hold 1 indicates the data takes two clocks (20ns) to stabilize on changing, and goes invalid immediately after changing (0ns).

The other pipelining (via _reg0 and _reg1) is basically irrelevant and could be removed. It would only be necessary for data alignment.