Delaying output of a module to close timing

Thanks for your response, kaz; this is much appreciated.

I will try using the same clock for the unsigned_mult64 module. I had switched to a slower clock in an attempt to close timing.

I am actually trying to emulate multiplication using 64-bit integers (as on a desktop computer), so I would like the output to also be 64 bit.

Here is the code that I am using for the pipelined multiplier. How would I add more pipeline stages inside the multiplier? What I am trying to do here is to infer a megafunction with a pipelined multiplication.

Is this the right way to do so or does the output have to be 128 bits?

Here is the code with timing issues:

module unsigned_mult64 ( a, b, clk, out);
// pipelined multiplier (4 cycles)
output  out;
input clk;
input signed  a;
input signed  b;
reg signed  a_reg0;
reg signed  a_reg1;
reg signed  a_reg2;
reg signed  b_reg0;
reg signed  b_reg1;
reg signed  b_reg2;
reg signed  out;
wire signed  mult_out;
assign mult_out = a_reg2 * b_reg2;
always @ (posedge clk)
begin
	// levels + 1 = pipeline = 4
	a_reg0 <= a;
	a_reg1 <= a_reg0;
	a_reg2 <= a_reg1;
	
	b_reg0 <= b;
	b_reg1 <= b_reg0;
	b_reg2 <= b_reg1;
	
	out <= mult_out;
end
endmodule