Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

delay

when doing an fpga synthesis with vhdl,what s the most appropriate way of delaying an assignment of a pin;that is signal a : std_logic; a <= '1' after 100 ns; like this ?
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
16 years ago

In addition to this counter method:

You could pass your signal through a shift register which would delay it by an integer number of clock cycles.

If you wanted a small delay then you could also buffer it with a number of LCELLS. You have to constraint Quartus not to remove these. You can also specify the minimum and maximum clock to output time of the signal. This would only only be suitable for delays of a few ns and you'd have to play with the number of LCELLS (there is a constraint to add a specified number of LCELLS in Quartus).