Delay variations of Altera FPGA primitives as PVT varies Options

Thanks Rysc for the excellent TimeQuest user guide that you are compiling. It gave me a lot of information that I was unaware of. The reason I was looking for information on delays of primitives was because I wanted to do a "minimum clock scheduling" of a design with just one clock. We usually talk about operations like addition, subtraction etc. and their delays in minimum clock scheduling. I know it sounds very academic, but this is a research problem that I am working on. I wanted to characterize delays of these modules (Adder, subtractor etc.) over PVT variations to so that I may include them in the minimum clock scheduling. I understand that any timing information arrived at this way won't be accurate. I was thinking that if I could have access to delay values over PVT variations for primitives, I might be able to characterize the delay of these modules too over PVT variations. Any suggestions would be greatly appreciated.:)