Delay variations of Altera FPGA primitives as PVT varies Options

There is no "table of values" or anything like that. TimeQuest calculates these values live. Note that timing models are not just a "look-up" of values. TimeQuest does a mini hspice-like simulation for many values, and there are many things that affect timing. That being said, if you put the primitives you want into a circuit, you can do timing analysis at the different timing corners. Also note that there are timing sub-models, so setup analysis and hold analysis give different values. (I discuss this in the TimeQuest User Guide on alterawiki)

Thanks Rysc for the excellent TimeQuest user guide that you are compiling. It gave me a lot of information that I was unaware of. The reason I was looking for information on delays of primitives was because I wanted to do a "minimum clock scheduling" of a design with just one clock. We usually talk about operations like addition, subtraction etc. and their delays in minimum clock scheduling. I know it sounds very academic, but this is a research problem that I am working on. I wanted to characterize delays of these modules (Adder, subtractor etc.) over PVT variations to so that I may include them in the minimum clock scheduling. I understand that any timing information arrived at this way won't be accurate. I was thinking that if I could have access to delay values over PVT variations for primitives, I might be able to characterize the delay of these modules too over PVT variations. Any suggestions would be greatly appreciated.:)

When you analyze a path in TimeQuest, you can get information on each piece.