delay of '< >' and '= !='

Understanding how things get synthesized will make you a better designer(on the flip-side, be careful of getting bogged down in the details). Every tool has their own synthesis algorithms and competes on results, which is one of the reasons its not opened up. You'll also find it very tuned to Altera-only architectures, which with the V series, uses the ALM for logic across the board(Stratix/Arria/Cyclone), which is pretty different than other architectures.