Delay involved in async propagation of input signal via Cyclone V SOC/FPGA die

We are using Cyclone V SOC along with Quartus Prime Standard Edition, and we would like to the know the delay involved for the input pin/signal (asynchronous) to propagate through the fpga/soc die without getting clocked in (not synchronized using sync registers) and come out via an output pin of the same fpga/soc.

How much would the delay be in this case?

We are seeing close to 12 ns in our case, is this real or are we doing something wrong?

What all factors contribute to this delay? Like input buffer delay for input pin/port, output buffer delay for output pin/port, internal propagation/routing delay, what else?

Why do I need answer to this question: I know you are thinking why we would not clock in (synchronous) the incoming async signal, we plan on doing this eventually but for now we are just trying to understand what is happening in our design for debugging an issue.

thanks in advance