Altera_Forum
Honored Contributor
Honored Contributordelay in verilog
How can I insert one delay in a program but not in a simulation in verilog!?
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Altera_ForumI want to add a delay in my code.
like in modelsim simulation we write " always@ (clock) begin # 5 a <= b; end " this adds a 5 time units delay to the signal. can we have something in QUATRUS Prime for simulation becoz this is not working in QUATRUS. can someone help me out?
