Delay between Input pin to output pin via single LE

Refer to the timing closure and optimization (http://www.altera.com/literature/hb/qts/qts_qii52005.pdf) datasheet for a wealth of information regarding timing.

This will discuss pin to register delays and register to pin delays as well as register to register timing. The key stats required to allow you to ensure a synchronous design meets timing.

However, I'm not sure it'll give you numbers you're after.

All I can confirm is that the figures you state TimeQuest offers sound about right. If you are simply using the FPGA as a buffer (something it's not very good at) then, depending on pin placement, I think you should expect anything from 2ns to in excess of 7ns. If the input pin happened to be a dedicated clock input, you might expect different figures.

Regards,

Alex