Honored Contributor
Honored Contributorthx guys i can see the problem with such designs now, i'm editing all project's block to be clocked by the 50MHz standard clock... very glad you had me notice the issue with such desings before expanding the system more. bellow is the displayer code edited the way you want. let me know that's the way you want it to be or if other enhancements can be made.
library ieee; use ieee.std_logic_1164.all; entity display_controller is port ( clk, reset_n : in std_logic; mc1, mc2 : in std_logic_vector(1 downto 0); fsensor1,fsensor2 : in std_logic_vector(2 downto 0); floor1_a, floor1_b : out std_logic_vector(6 downto 0); floor2_a, floor2_b : out std_logic_vector(6 downto 0); mc1_a,mc1_b,mc2_a,mc2_b : out std_logic_vector(6 downto 0)); end entity display_controller; architecture behavioral of display_controller is signal f1,f2 : std_logic_vector (6 downto 0); signal m1,m2 : std_logic_vector (13 downto 0); signal initial : std_logic := '0'; -- used for initialization begin process (clk) begin if rising_edge(clk) then initial <='1'; end if; end process; process (mc1,reset_n,clk) begin if rising_edge(clk) then if (initial = '0') then m1 <= "11111111111111"; -- clear display elsif (mc1="10") then m1 <= "01000010101011"; -- display: dn elsif (mc1="11") then m1 <= "10000010001100"; -- display: up else m1 <= "01111110111111"; -- display: -- end if; end if; end process; process (mc2,reset_n,clk) begin if rising_edge(clk) then if (initial = '0') then m2 <= "11111111111111"; -- clear display elsif (mc2="10") then m2 <= "01000010101011"; -- display: dn elsif (mc2="11") then m2 <= "10000010001100"; -- display: up else m2 <= "01111110111111"; -- display: -- end if; end if; end process; process (fsensor1,reset_n,clk) begin if rising_edge(clk) then if (initial = '0') then f1 <= "1111111"; -- clear display elsif (fsensor1="001") then f1 <= "1111001"; -- display: 1 elsif (fsensor1="010") then f1 <= "0100100"; -- display: 2 elsif (fsensor1="011") then f1 <= "0110000"; -- display: 3 elsif (fsensor1="100") then f1 <= "0011001"; -- display: 4 else f1 <= f1; -- latch the output end if; end if; end process; process (fsensor2,reset_n,clk) begin if rising_edge(clk) then if (initial = '0') then f2 <= "1111111"; -- clear display elsif (fsensor2="001") then f2 <= "1111001"; -- display: 1 elsif (fsensor2="010") then f2 <= "0100100"; -- display: 2 elsif (fsensor2="011") then f2 <= "0110000"; -- display: 3 elsif (fsensor2="100") then f2 <= "0011001"; -- display: 4 else f2 <= f2; -- latch the output end if; end if; end process; mc1_a <= m1(6 downto 0); mc1_b <= m1(13 downto 7); mc2_a <= m2(6 downto 0); mc2_b <= m2(13 downto 7); floor1_a <= f1; floor1_b <= "1111111"; floor2_a <= f2; floor2_b <= "1111111"; end architecture behavioral; thx again guys it's really kind of you to give help in such short notice, peace :)
