Forum Discussion
Altera_Forum
Honored Contributor
12 years agoIm glad this works for you now. But adding to what others have said, combinatorial logic and latches are also prone to glitches, poor timing and temperature variations. Its quite common for a circuit like this to work fine, then the next time you compile it, it doesnt work at all, probably because the routing delays have got too long on that build (ok, maybe not for a simple circuit like this, but fill the chip with say 50%, and you'll have problems). Timequest cannot analyse async logic and latches, so you can run into these problems easily.
Solution, go with synchronous design (thats how FPGAs are architected)