Default latched outputs values

your design is all combinatorial with some latches. Not a typical fpga design but fair enough as good as it works.

You can either clock all changes or a quicker way is to have internal reset as clocked register:

signal reset_int : std_logic := '0';

process(clk)

begin

if rising_edge(clk) then

reset_int <= '1';

end if;

end process;

then connect reset_int with reset_n. That way the latches will start as all ones. for example:

if reset_int = '0' do this

elsif reset_n = '0' do this...etc

If the tool optimised away reset_int register then you need to tackle it.