Honored Contributor1- In Altera FPGAs currently I am using Cyclone 4 is there a dedicated clock output pin?
2- Are we encouraged to use dedicated clock output pin or can we use some random I/O register(in the pad) as a clock
Honored ContributorThere's a dedicated pair of clock ouput pins assigned to each Cyclone PLL. You are encouraged to use it preferably as clock output by the FPGA timing specification, which assures less jitter and uncertainty for the dedicated pins. You can however use any I/O pin if suitable for your design.
Honored ContributorDear FvM
Assume that I do not use PLL in the design Question: If I plan to use the dedicated pair of clock pins; do I have to put the clock signal into a PLL before sending out? Or just assigning the signal to the pin and not instantiating PLL is good enough for me.Honored ContributorIf not connected to a PLL, the clock ouput pins will work as regular I/O. If you don't utilize PLLs in your design, there's no purpose of referring to dedicated clock outputs.
