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Altera_Forum
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12 years ago

Debugging TDO on Cyclone V

Hello, I am making my first attempt at a custom Cyclone V 5CEBA4U15 board after using a rival FPGA vendor for several years, so I have probably made some rookie mistakes. The JTAG chain is bro...
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Altera_Forum
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12 years ago

Hi Dave,

Thank you very much for your suggestions; they pointed me in the right direction and quickly led to the problem. I had failed to understand the requirements of VCCPD on each bank. I mistakenly thought they only applied to bank 3 (which has the external JTAG signals), so I was trying to run bank 5 with VCCPD = VCCIO = 1.8v, which led to the behavior described above.

The VCCPD pads are tied to VCCIO on an inaccessible layer on that bank, but I switched the entire VCCIO=VCCPD net up to 3.3v and now the JTAG chain initializes successfully. This requirement is listed on pages 5-8 and 7-5 of the manual, but I failed to grasp the concept of an i/o pre-driver supply.

Thanks again for your help.

Regards,

Morgan