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I happen to have a microcontroller on this board connected to nCONFIG, so I now have it wait 500ms after power-up and then apply a 100ms negative pulse on nCONFIG. This looks fine on the scope.
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Ok, that should satisfy the power-on requirements (at least it would for earlier generation devices, I have not read the Cyclone V handbook in detail).
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Unfortunately, the TDO behavior is the same.
nSTATUS never releases high; it stays continually low during and after power is applied to the board. From the state diagram on page 7-4 of the Cyclone V manual, I'm not sure if this means that the chip is in the "power up," "reset," or "configuration error handling" state. Is there a way to determine this?
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I'd recommend focusing on nSTATUS being low to start with. This signal should release after power-on-reset and nCONFIG deassertion. The fact that it is low indicates some low-level hardware error that may preclude the JTAG actually working.
Do you have multiple boards? Check if this is a common problem.
I'd start with the obvious checks (though you may have already done this). Look at the power supply voltages, and impedance of each power segment. If you have multiple boards, then compare their impedance. Quite often the impedance values will not be identical, but if you measure >1k on several boards, and <100-ohm on one, you can suspect it as possibly having an issue.
Do you have a Cyclone V reference board? If you do, look at its power and configuration scheme. Measure its nSTATUS and nCONFIG signals at power-on. If you do not have a Cyclone V board, download a Altera kit installation file, and install it. Inside you'll find its schematic. Look at the schematic and see if anything weird jumps out at you.
Cheers,
Dave
Honored Contributor
