Forum Discussion

Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Debugging TDO on Cyclone V

Hello, I am making my first attempt at a custom Cyclone V 5CEBA4U15 board after using a rival FPGA vendor for several years, so I have probably made some rookie mistakes. The JTAG chain is bro...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Hi Dave,

Thank you for the quick response.

I happen to have a microcontroller on this board connected to nCONFIG, so I now have it wait 500ms after power-up and then apply a 100ms negative pulse on nCONFIG. This looks fine on the scope. Unfortunately, the TDO behavior is the same.

nSTATUS never releases high; it stays continually low during and after power is applied to the board. From the state diagram on page 7-4 of the Cyclone V manual, I'm not sure if this means that the chip is in the "power up," "reset," or "configuration error handling" state. Is there a way to determine this?

Regards,

Morgan