Debugging NIOS out of reset

Hi,

I’m having a problem with the NIOS processor in the design. It looks like the Avalon bus is getting stuck on different memory accesses. For a long time it was on the instruction master but the last few builds it’s been on the data master. I’ve been changing settings in the .qsys system as well as in the BSP and some of them are changing where the issue occurs but I’m constantly seeing something like the attached image where the NIOS is attempting a read but waitrequest is held high forever. In the case below, the data master is attempting to read from the EPCQ avl_csr. But I’ve also seen it happening when the instruction master is attempting to read from the on chip ram.

I’ve attempted some debugging with system console and a JTAG to Avalon master. I tried the following commands:

% set jd_path [lindex [get_service_paths jtag_debug] 0]
/devices/10AX048E(1|2|3|3ES|4|4ES)|..@1#USB-0/(link)/JTAG/(110:132 v1 #0)/phy_0
% jtag_debug_reset_system $jd_path

any suggestion?