Honored Contributor
Honored ContributorA watchdog is a component (outside or inside FPGA) that reset the board after a specified timeout. It must be regulary cleared by a function in the embedded software to prevent reset.
By this way, if a "bug" occure and hangs the program, after the watchdog timeout, your system is restarted and "continue" to work. I don't use any software to analyse the code to detect memory leak, buffer overflow... since NIOS II is not an usual environment (like Unix) : the memory is determined by Qsys/sopc. I advice to write a good code : I know how much memory takes a structure, write interrupt routines short as possible, non blocking functions... Why do you use Visual Studio. why don't you use the Eclipse NIOS II SBT supplied with QUARTUS ? Some versions of Visual Studio does NOT respect C standard (one developer has to write numeral# IFDEF to write code specially to Visual Studio).
