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Altera_Forum's avatar
Altera_Forum
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14 years ago

DE2 board PLL

Is there a way with the web edition of Quartus II 11.1 to get a 1Mhz clock in the PLL? I keep getting an error saying that it cannot divide that large of a number. Is there a work around? Than...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
14 years ago

For frequencies that low, its more typical to generate a 1MHz 'enable' signal, and use that to control the logic. Alternatively, you could use a counter to divide a higher-frequency clock to generate the 1MHz clock. Just make sure to setup the TimeQuest constraints correctly, I believe the command is something like create_generated_clock. Search the forum for discussions by Rysc for TimeQuest suggestions.

Cheers,

Dave