DE2 Audio Codec Programming

Good day

I still have not found it out.

My development board (altera cyclone II) passes the input(linein) straight to the output (lineout) irrespective of the bypass setting. Does anybody know how to prevent the input displaying on the output.

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Good Day Everyone

The g00_audio_interface.vhd code does not process the input of audio, as stated in the pretext information.

Does anyone know how the input can be done? (in VHDL code)

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I also need to know how. should you find help elsewhere, please let me know n I sure will do the same...

Kind

Regards

Good Day Everyone

The g00_audio_interface.vhd code does not process the input of audio, as stated in the pretext information.

Does anyone know how the input can be done? (in VHDL code)

Kind

Regards

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I have tested this on both the DE1 and DE2 boards.

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Hi, I am wondering how you tested it. Did you send random values on your data lines? I'm trying yo used this code on a different development board but the principles are the same.

Regards,

Hunter

Thanks for your vhdl code jjclark. It is really helpful.

I have set it up and it works perfect. I am now trying to feed line in from the audio codec. But am having trouble, as the output has a lot of noise. Im guessing its got something to do with my timing?

Would you be able to attach an example of line in? That would be very appreciated.

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Hi,

I am engg student.I are working on SOPC baesd speech to text conversion.I am confused with how to to program audio codec for Audio to Digital conversion for input from microphone and give it to FPGA.

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Go throw the data sheet of codec configure the codec registor ,the sound digital data will be available on ADCDAT of codec

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Hello Mr. Khan, you could use one of the PLLs on the Cyclone II chip to convert from 50MHz to 24MHz. Or you could just implement a simple counter. You could just divide by 2 (giving 25MHz). This would result in a sampling rate slightly more than 48KHz, but depending on your application would probably not make an audible difference.

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Dear sir i have done the intitialization of the codec registor by using the 50Mhz crystal i am getting ack , sir i am not getting whether xclk i.e the master clock of codec must require to fetch the data from LR chanal please sugest the logic for sound fetching & more about the DSP mode of codec.