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What entity is going to look at the flag you're intending to raise? A Nios processor? Or some other internal logic?
Accessing external SSRAM won't incur any 'significant' delay. Unless you're hoping to operate your logic/Nios at a very high clock frequency (which will be tricky with Cyclone II), the SSRAM on that board will operate at the same frequency as your logic. SSRAMs offer single (or double) clock cycle accesses. So any flag you raise is only going to be high for 1 or 2 clock cycles. I accept burst accesses are slightly longer, but arguably still not significant.
However, if you're using Nios, it will handle these accesses without the need for a flag. If you're writing your own logic then you will design your SSRAM controller in such a way that the logic always knows where in the SSRAM access cycle it is, and when it's finished.
Cheers,
Alex
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Given that this is for a processor design course, I'll probably have to handle this with my own controller, using the SRAM input/output pins.
Is there a specific document that identifies how many clock cycles it takes to read and write (specifically using the 50MHz clock), or will I need to develop a cycle by cycle verification of the process?
Additionally, do you know if there's an SRAM content viewer/editor built into Quartus II to make verification of data input/output easier?
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