DE2-115 using GPIOs

I am trying to build a simple example which uses a statemachine to change a bit and then send that bit as an output to the GPIO. I am using a DE@-115 board with Quartus IIversion 13. I am using a Saleae logicdevice to monitor the GPIO outputs. Attachedis my code.

Things that work:

Switches control LEDR.

KEY controls LEDG.

Assigning a SW(2) to the GPIOoutput myBit2 works. I can see theoutput change when I flip the switch during capture.

Assigning a KEY to myBit works.

What doesn’t work:

Assigning clk to myBit

Assigning data to myBit2 fromthe state machine

Task:

To control a GPIO output logiclevel with software.

LIBRARY ieee;
USE ieee.std_logic_1164.all;
entity part is
  Port ( clk : in STD_LOGIC:='0';
     SW : IN STD_LOGIC_VECTOR(17 DOWNTO 0);
     LEDR : OUT STD_LOGIC_VECTOR(17 DOWNTO 0):="000000000000000000"; -- red LEDs
       LEDG : OUT STD_LOGIC_VECTOR(8 DOWNTO 0):="000000000"; -- green LEDs
       KEY : IN STD_LOGIC_VECTOR(3 DOWNTO 0);
       myBit, myBit1, myBit2, myBit3 : out STD_logic); --GPIO 0, 1, 2, 3
 end part;
 architecture Behavioral of part is
 signal clk1 : STD_LOGIC:='0';
 signal clkout:std_logic:='0'; 
 
 --clk <= clk;
 type state is(state1,state2,state3,state4,state5,state6,state7,state8,state9,state10);
 signal current_state,next_state:state;
 signal data:std_logic:='1';
 begin
Clock : process(clk1, clkout) 
 begin 
 if clk1 <= 'U' then clk1 <= '0' after 2 us;
 else clk1 <= not clk1 after 2 us;
 end if;
 if clkout <= 'U' then clkout <= '0' after 2 us;
 else clkout <= not clkout after 2 us;
 end if;
 end process; 
 process(clkout) 
 begin 
 current_state<=next_state; 
 end process; 
 process(current_state,next_state) 
 begin 
 case current_state is 
 when state1=> 
 data <='0'; 
 next_state<=state2; 
 when state2=> 
 data <='1'; 
 next_state<=state3; 
 when state3=> 
 data <='1';
 next_state<=state4; 
 when state4=> 
 data <='1';
 next_state<=state5; 
 when state5=> 
 data <='1';
 next_state<=state6; 
 when state6=> 
 data <='1';
 next_state<=state7; 
 when state7=> 
 data <='0'; 
 next_state<=state8; 
 when state8=> 
 data <='0';
 next_state<=state9; 
 when state9=> 
 data <='1';
 next_state<=state10; 
 when state10=> 
 data <='1';
 next_state<=state1; 
 end case; 
 myBit3 <= data;
 end process; 
 
 LEDG(7) <= KEY(3);
 LEDG(5) <= KEY(2);
 LEDG(3) <= KEY(1);
 LEDG(1) <= KEY(0); 
 LEDR(0) <= SW(0);
 LEDR(1) <= SW(1);
 LEDR(2) <= SW(2);
 LEDR(3) <= SW(3);
 myBit <= SW(0); 
 myBit2 <= SW(2);
 end Behavioral;