DE2 : GPIO output waveforms

Your code may not involve syntax errors in terms of Verilog language rules. Verilog (or VHDL) aren't restricted to describe circuits synthesizable in actual hardware. It's your job to use only sysnthesizable constructs.

As I said, I thinks it's not primarly a Verilog problem. The problem is about understanding logic hardware design. Of course there's another point of using the right syntax for synthesizable Verilog. You'll find it e.g. in the Quartus Verilog templates.