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Altera_Forum
Honored Contributor
Honored ContributorDE2 : GPIO output waveforms
Hi..i am having a problem and don't have any idea how to solve this problem. I had do the simulation using modesim and working fine. However when I download the code to DE2 board with Cyclone II, the...
Altera_ForumHonored Contributor
Honored ContributorYour code may not involve syntax errors in terms of Verilog language rules. Verilog (or VHDL) aren't restricted to describe circuits synthesizable in actual hardware. It's your job to use only sysnthesizable constructs.
As I said, I thinks it's not primarly a Verilog problem. The problem is about understanding logic hardware design. Of course there's another point of using the right syntax for synthesizable Verilog. You'll find it e.g. in the Quartus Verilog templates.
