DE115 Lab 3 part 2 question Clk does not exist in primitive error

I compiled a project with your two files in Modelsim and it went with no errors, so your problem isn't in the VHDL code. Check that your project is set correctly (i.e. that you are compiling both files, and that they are the right ones).

vlib work
vcom Lab3.vhd
vcom DLatch.vhd
vsim work.Lab3b

Modelsim > do lab3.tcl
#  Model Technology ModelSim ALTERA vcom 10.0c Compiler 2011.09 Sep 21 2011
#  -- Loading package STANDARD
#  -- Loading package TEXTIO
#  -- Loading package std_logic_1164
#  -- Compiling entity Lab3b
#  -- Compiling architecture Structural of Lab3b
#  Model Technology ModelSim ALTERA vcom 10.0c Compiler 2011.09 Sep 21 2011
#  -- Loading package STANDARD
#  -- Loading package TEXTIO
#  -- Loading package std_logic_1164
#  -- Compiling entity DLatch
#  -- Compiling architecture Structural of DLatch
#  vsim work.Lab3b 
#  Loading std.standard
#  Loading std.textio(body)
#  Loading ieee.std_logic_1164(body)
#  Loading work.lab3b(structural)
#  Loading work.dlatch(structural)