DE1 board to PC communication

The state machine fills in for the NIOS core that Altera recommends as the manager for the Jtag Atlantic interface through the USB port to a PC host application. The NIOS core is an Altera IP and has cost which include limitations for use and distribution attached. The state machine solution is a small footprint solution free of IP limitations.

On Host side you need to open the Jtag atlantic connection and then you can send ascii strings to the DE board or read strings that the board sends you back. These strings can be command strings etc. I provided the FPGA side and PC code example (vhdl, and C++) for command parsing and for sending responses back to the host with some examples.

Each user can make up his own set and direct the FPGA hardware accordingly. I have a more specific version for one of my FPGA applications. It can set some memory address lines, read status lines (to augment the on-board LEDs and perform other control functions.