Honored Contributor
Honored ContributorI am trying to design a PC to DE board communication/control interface. I have found that the jtag_atlantic.dll can be used from the PC side to talk to the jtag_uart on the FPGA side. However all the system samples using the jtag_uart include a NIOS processor to handle the communications on the FPGA side.
I have designed a state machine instead that is supposed to respond to the jtag_uart Irq events. In this way I hope to achieve a fast response an a small implementation. I have built a small C++ application which is based on the terminal example for the jtag_atlantic dll which detects the USB blaster and sends a character string to the FPGA. The USB LED on the DE board lights up each time I send a string from my utility - so a signal is getting to the board. Unfortunately - I cannot detect any Irq events from the jtag_uart (in my state machine I set up an LED to light up when Irq goes high as a debug signal). Because the control app on the PC used the USB blaster I can't use the logic analyzer to debug the signals in the FPGA. does anyone have ideas how to solve this problem?
