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Altera_Forum
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10 years ago

DE0_NANO_SOC LVDS Problem

Hello,

We are currently using the DE0_NANO_SOC from Terasic (http://www.terasic.com.tw/cgi-bin/page/archive.pl?language=english&no=941) for our system, using the 5CSEMA4U23C6 FPGA.

We running into some issues trying to set up our pins.

Our system requires 8 pairs of LVDS RX signals, 6 channels of Data (AFE_DATA) and two clocks (AFE_FCLK and AFE_DCLK).

We are planning to use the GPIO pins on the DE0_NANO_SOC as our input for these signals.

I managed to get the 6 pairs of AFE_DATA Signal connected correctly to the GPIO_0 side, all 6 pairs of them connected to the FPGA Bank 3B pins.

However, I am having trouble with FCLK and DCLK. As the GPIO pins that are connected to Bank 3B has only 6 pairs of LVDS RX, I have to go to the other banks (3A, 4A) for RX pins. However, when I tried to set the FCLK and DCLK pins to either Bank 3A or 4A pins, I get the following errors

Error (169029): Pin AFE_DCLK is incompatible with I/O bank 4A. Pin uses I/O standard LVDS, which has a VCCIO requirement incompatible with that bank's VCCIO setting or its other pins that use VCCIO 3.3V.

Error (169029): Pin AFE_FCLK is incompatible with I/O bank 4A. Pin uses I/O standard LVDS, which has a VCCIO requirement incompatible with that bank's VCCIO setting or its other pins that use VCCIO 3.3V.

Here's the info from my assignment editor

Ok AFE_FCLK Location PIN_AC22 Yes

Ok AFE_FCLK I/O Standard LVDS Yes DE0_NANO_SOC

Ok AFE_FCLK Input Termination Differential Yes DE0_NANO_SOC

Ok AFE_FCLK(n) Location PIN_AC23 Yes

Ok AFE_FCLK(n) I/O Standard LVDS Yes DE0_NANO_SOC

Ok AFE_FCLK(n) Input Termination Differential Yes DE0_NANO_SOC

Ok AFE_DCLK Location PIN_AD23 Yes

Ok AFE_DCLK I/O Standard LVDS Yes DE0_NANO_SOC

Ok AFE_DCLK Input Termination Differential Yes DE0_NANO_SOC

Ok AFE_DCLK(n) Location PIN_AE22 Yes

Ok AFE_DCLK(n) I/O Standard LVDS Yes DE0_NANO_SOC

Ok AFE_DCLK(n) Input Termination Differential Yes DE0_NANO_SOC

Please help!

Jack Zhang

2 Replies

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    10 years ago

    Bank 4A is powered from 3.3V on the DE0-Nano-SOC. LVDS requires 2.5V. So, you probably have a mix of I/O standards, all connected to bank 4A, that require different supply voltages. So, Quartus can't solve your puzzle and throws out that error.

    Unfortunately, you can't change the voltage applied to this bank, which is a shame given it only handles expansion headers.

    However, the fact that this bank doesn't support anything but expansion headers offers a way around this - assuming you're not connecting anything to the Arduino headers.

    In your Quartus project, remove all I/O constraints relating to this bank. Then add your clock input signals as LVDS.

    Quartus will then assume that the bank is to be powered from 2.5V. Confirm this via the .pin file following compilation. You can drive LVDS into a bank powered at 3.3V.

    Regards,

    Alex