DE0-Nano-SoC: How HPS(ARM) recognizes f2h_irq0 or f2h_irq1 interrupts from FPGA

I designed a block in Verilog. When data processing is finished, this FPGA block sends an interrupt signal to HPS using one of dedicated interrupt line: f2h_irq0 or f2h_irq1. The question is how HP...