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Altera_Forum's avatar
Altera_Forum
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8 years ago

DE0-NANO Board SDC file and PLL

Hallo

I have a DE0-NANO board. There is a on board 50 MHz oscillator on the board which works as the clock to the FPGA. Now suppose i want to run my design at 30 MHz. So i write a SDC file like the following, would this work? I mean would this already create a pll which will run my design at 33 MHz when i download it on the FPGA?

# Constrain clock port clk with a 30-ns requirement

create_clock -period 33 [get_ports clk]

# Automatically apply a generate clock on the output of phase-locked loops (PLLs) # This command can be safely left in the SDC even if no PLLs exist in the design

derive_pll_clocks

derive_clock_uncertainty

# Constrain the input I/O path

set_input_delay -clock clk -max 0.5 [all_inputs]

set_input_delay -clock clk -min 0.1 [all_inputs]

# Constrain the output I/O path

set_output_delay -clock clk -max 0.5 [all_outputs]

set_output_delay -clock clk -min 0.1 [all_outputs]

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    8 years ago

    Changing the SDC file will not change the FPGA design or the board or the behaviour of any of the components on the board. There is a fixed 50MHz oscillator on the Nano.

    If you want to run everything at 30MHz then you either need to de-solder 50MHz oscillator and replace it with a 30MHz part - don't do this - or, far more practically, use one of the PLLs in your FPGA to generate the 30MHz clock from the 50MHz. Use the IP catalogue in Quartus to locate a PLL and configure it to your needs. Then instantiate it in your design.

    The 'derive_pll_clocks' in your SDC file will then deal with everything required to check that the design will run at the revised frequency.

    Cheers,

    Alex