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Altera_Forum
Honored Contributor
Honored ContributorDE0-NANO Board SDC file and PLL
Hallo I have a DE0-NANO board. There is a on board 50 MHz oscillator on the board which works as the clock to the FPGA. Now suppose i want to run my design at 30 MHz. So i write a SDC file like...
Altera_ForumHonored Contributor
Honored ContributorChanging the SDC file will not change the FPGA design or the board or the behaviour of any of the components on the board. There is a fixed 50MHz oscillator on the Nano.
If you want to run everything at 30MHz then you either need to de-solder 50MHz oscillator and replace it with a 30MHz part - don't do this - or, far more practically, use one of the PLLs in your FPGA to generate the 30MHz clock from the 50MHz. Use the IP catalogue in Quartus to locate a PLL and configure it to your needs. Then instantiate it in your design. The 'derive_pll_clocks' in your SDC file will then deal with everything required to check that the design will run at the revised frequency. Cheers, Alex
