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mark_lee's avatar
mark_lee
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

DDR4 can not be read

hi team

There are an ddr4_ctrl modular in my design, I add it in the qsys , connect it to two modular by avalon Bus. One is the PCIE , the other is my application modular (APP) . run Qsys to Genarat HDL . a "mm_interconnect_3 " modular will be generated. As below show:

I run the design in my board , PCIE can read and write the DDR4 chip , but my application modular can not read and write the DDR4 chip . single Tap get the "nano_adrv9009_0_m1_waitrequest" keep " high" .

waht is the problem

3 Replies

  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    4 years ago

    Hi Mark,


    May I know how do you perform this R/W operation?


    I just curious where are all this components come from, is it from Intel IP?


    Just for sanity check, is there any connectivity issue between the PCIE modular and APP modular?


    Is your design are working as expected in the simulation?


    Regards,

    Adzim


  • AdzimZM_Altera's avatar
    AdzimZM_Altera
    Icon for Regular Contributor rankRegular Contributor
    3 years ago

    We do not receive any response from you to the previous question/reply/answer that I have provided. This thread will be transitioned to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.