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Altera_Forum's avatar
Altera_Forum
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12 years ago

DDR3 UniPHY problems

Hello, I am trying to incude a DDR3 UniPHY Controller megacore to my design, but I am experiencing several issues. I am working on a TR4 development kit (TERASIC) based on the STRATIX IV FPGA (...
Altera_Forum's avatar
Altera_Forum
Icon for Honored Contributor rankHonored Contributor
12 years ago

Hi Giovanni,

you have to launch a .tcl script to complete the constraint file

for the DDR3 pins. It is something like <your_controller_name>_p0_pin_assignments.tcl

hope this could solve your problem,

regards,