DDR3 UniPHY IP synthesis problem

Messages such as this indicate there are portions of the design that have no bearing on other parts of the logic or signal outputs. As they don't drive anything, they may as well be removed.

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my ddr3_project working

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I take this to mean the project is doing everything you expect it to do? This is what I'd expect. I don't think you should expect the result to be that certain commands/data won't be transmitted to the external memory.

If the interface ISN'T behaving as expected and you believe this logic shouldn't be removed, then you need to revisit your design, and specifically consider how the IP is connect up.

Regards,

Alex