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Altera_Forum's avatar
Altera_Forum
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12 years ago

DDR3 UniPHY IP synthesis problem

Hi!

When I tried to compile the example_project generated in the DDR3 UniPHY IP, I found some warnings in the synthesis procedure. This one confused me:

Warning (14285): Synthesized away the following PLL node(s):

- Warning (14320): Synthesized away node "ddr3_example_if0:if0|ddr3_example_if0_pll0: pll0|pll_mem_clk"

- Warning (14320): Synthesized away node "ddr3_example_if0:if0|ddr3_example_if0_pll0: pll0|afi_phy_clk"

does it matter my ddr3_project working?

I'm not familiar with the intersignals between the memory controller portion to the UniPHY portion, but I think if afi_phy_clk is synthesized away, some commands and data cannot transmit to the external memory.

Thanks a lot!

BR,

Song.

1 Reply

  • Altera_Forum's avatar
    Altera_Forum
    Icon for Honored Contributor rankHonored Contributor
    12 years ago

    Messages such as this indicate there are portions of the design that have no bearing on other parts of the logic or signal outputs. As they don't drive anything, they may as well be removed.

    --- Quote Start ---

    my ddr3_project working

    --- Quote End ---

    I take this to mean the project is doing everything you expect it to do? This is what I'd expect. I don't think you should expect the result to be that certain commands/data won't be transmitted to the external memory.

    If the interface ISN'T behaving as expected and you believe this logic shouldn't be removed, then you need to revisit your design, and specifically consider how the IP is connect up.

    Regards,

    Alex