DDR3 timing errors on Cyclone V

Closing timing on a design using the 5CGTFD9E5F35C7, getting a few (17) setup failures on a DDR3 controller core; launch and latch clock are different, but both are part of DDR3 core. From: and to: nodes are also all internal to core. An example:

slack: -3.404

from node: ddr3_v20:ddr3_v20_inst|ddr3_v20_0002:ddr3_v20_inst|ddr3_v20_s0:s0|altera_mem_if_sequencer_cpu_cv_synth_cpu_inst:cpu_inst|W_alu_result[15]

to node:

ddr3_v20:ddr3_v20_inst|ddr3_v20_0002:ddr3_v20_inst|ddr3_v20_s0:s0|sequencer_scc_mgr:sequencer_scc_mgr_inst|scc_parallel

launch clock:

ddr3_v20_inst|ddr3_v20_inst|pll0|pll6~PLL_OUTPUT_COUNTER|divclk

latch clock:

ddr3_v20_inst|ddr3_v20_inst|pll0|pll7~PLL_OUTPUT_COUNTER|divclk

relationship: 0.000

clock skew: -0.599

data delay: 2.735

Note that launch and latch edges are coincident (doesn't seem quite fair does it?). The clock frequencies seem to be quite low (<= 50 MHz?). Closure recommendations provided by Timing Analyzer all seem to ask for changes to the core design (move nodes - not sure exactly what that means, duplicate nodes, ensure launch and latch frequencies are exact multiples, reduce levels of logic).

I would think that the SDC files created by Platform Designer would have constrained the core sufficiently.

Suggestions?

Thanks.