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Seadog's avatar
Seadog
Icon for Occasional Contributor rankOccasional Contributor
4 years ago

DDR3 timing errors on Cyclone V

Closing timing on a design using the 5CGTFD9E5F35C7, getting a few (17) setup failures on a DDR3 controller core; launch and latch clock are different, but both are part of DDR3 core. From: and to: ...
AdzimZM_Altera's avatar
AdzimZM_Altera
Icon for Regular Contributor rankRegular Contributor
4 years ago

I’m glad that your question has been addressed, I now transition this thread to community support. If you have a new question, feel free to open a new thread to get the support from Intel experts. Otherwise, the community users will continue to help you on this thread. Thank you.